COMPUTER ARCHITECTURE – 2022/2023 PGD PAST QUESTION & ANSWER

This Article shows the Past question and Answer workings for the Post Graduate Diploma program of Federal Polytechnic Bauchi in Affiliation with Joseph Sarwvan Tarka University, Markurdi.

This Past Question is for the year 2022/2023 Academic Session, and it’s helpful for those currently writing their on going exams in the department of Computer Science.

N.B – These questions and answers are uploaded only as a guide and ease for your studies.

THE FEDERAL POLYTECHNIC, BAUCHI

DIRECTORATE OF UNIVERSITY AFFILIATIONS AND LINKAGES

IN AFFILIATION

WITH JOSEPH SARWUAN TARKA UNIVERSITY MAKURDI

END OF SECOND SEMESTER EXAMINATION  2022/2023 ACADEMIC SESSION

PROGRAMME: PGD Computer Science

COLLEGE: College of Physical Sciences

DEPARTMENT: Computer Science

COURSE TITLE: Computer Architecture

COURSE CODE: CMP 712

INSTRUCTION: Answer any FIVE questions

TIME: 2 Hour 30 minutes

MAXIMUM EXAMS MARKS: 70%

1. a) State the full meaning of the following abbreviations: i)ALU  ii) MDR  iii) RISC iv) CISC v) PLAs

b) An Itanium processor has 64-address lines. Determine:

i) the size of the data lines.

ii) the size of memory addressable by the processor.

c) Control signals indicate the type of action taking place on the system bus. State any five of control signals that you know.

2. a) State the five stages of instruction execution.

b) Computer A runs program gcc in 3.2 seconds. Computer B runs the same program in 2.9 seconds. Which computer has a better performance and by how much? What about computer C which runs the program in 3.1 seconds?

3, a) What do you understand by pipelining?

b) Consider a nonpipelined machine with 5 execution steps of lengths 50 ns, 20 ns, 50 ns. 20 ns and 50 ns,

i. Find the instruction latency on this machine.

ii. How much time does it take to execute 100 instructions?

Suppose we introduce pipelining on this machine. Assume that when introducing pipelining, the clock skew adds 5ns of overhead to each execution stage.

iii. What is the instruction latency on the pipelined machine?

iv. How much time does it take to execute 100 instructions?

v. What is the speedup obtained from pipelining?

4. a) With the aid of a diagram, explain what you understand by virtual memory?

b) Using load/Store architecture of a processor, write low level instruction for the following C++ statement:

a=b+c *d-e+f+a;

5. Consider the following C++ statement:

A =b+c *d-e+f+a;

Required:

a) Using Three-Address machine write assembly codes for the C++ statement.

b) Using Two-Address machine write assembly codes for the C++ statement.

c) Using memory access as metrics, compare the Three-Address machine with the Two-Address machine

6. Consider the following C+-+ statement:

A= b+c d-e+f+a;

Required:

a) Using One-Address machine write asymbly codes for the C++ statement.

b) Using Zero-Address machine, write assembly codes for the C++ statement.

c) Using memory access as metrics, compare the One-Address machine with the Zero-Address

machine.

7. a) What do you understand by addressing mode?

b) State three places where operand may be located.

c) State and explain any three addressing modes used by Pentium processor.

1. a) i. ALU — Arithmetic Logic Unit

ii) MDR  — Memory Data Register

iii) RISC — Reduce Instruction Set Computing

iv) CISC — Complex Instruction Set Computing

v) PLAs — Programmable Logic Arrays

b) Itanium processor 64 address line

i) the size of the data lines.

N.B the size of the data bus is always times two the size of the address bus.

If 64-bit address = The size of the data bus

= 2 x 64 = 128bit Ans.

ii)  the size of memory addressable by the processor.

The number of locations of the devices that can be referenced

= 2³² => 2³⁰ x 2²

Recall, 2³⁰ = 1MB

2² = 4

Therefore: 1MB x 4 = 4MB Ans.

So, we have;

Start address = 0000 0000 0000 0000⁴

Last address = FFFF FFFF FFFF FFFF⁴

c) i. Clock Signal (CLK) ii. Read Signal (RD) iii. Write Signal (WR) iv. Load/Store Signal (LD/ST) v. Enable Signal (EN)

2. a)i. Instruction Fetch (IF): This retrieve instruction from memory, update program counter (PC) and store instruction in Instruction Register (IR).

ii. Instruction Decode (ID): This Decode instruction opcode, Determine instruction type (e.g., arithmetic, load/store) and then Extract operands.

iii. Operand Fetch (OF): This retrieve operands from registers or memory and load operands into registers.

iv. Execution (EX): This perform arithmetic/logical operation, calculate address for memory access and update registers or memory.

v. Write Back (WB): This store results in registers or memory, update status flags (e.g., carry, zero) and complete instruction execution.

b) Computer B runs the program 0.3 seconds faster than Computer A. (3.2 – 2.9 = 0.3)

Performance difference:

(3.2 – 2.9) / 3.2 = 0.09375

(0.09375 x 100% = 9.375%)

Therefore: Computer B is approximately 9.38% faster than Computer A.

Computer B runs the program 0.2 seconds faster than Computer C. (3.1 – 2.9 = 0.2)

Performance difference:

(3.1 – 2.9) / 3.1 = 0.0645

(0.0645 x 100% = 6.45%)

Computer B is 6.45% faster than Computer C.

Therefore: Computer B has better performance than the other two computers (A & C) because it is 9.38% faster than Computer A and 6.45% faster than Computer C.

3. a) pipelining is a techniques using computer architecture to improve the performance of a processor.

b) i. Instruction Latency: Instruction latency is the time taken to complete one instruction.

Execution steps and durations: 50 ns, 20 ns, 50 ns, 20 ns, 50 ns

Total instruction latency =

50 + 20 + 50 + 20 + 50 = 190 ns (Ans)

ii. Time to Execute 100 Instructions: Since the machine is non-pipelined, each instruction is executed sequentially.

Time to execute 100 instructions:

190 ns/instruction × 100 instructions = 19,000 ns

Convert to milliseconds:

19,000 ns = 0.019 ms (milliseconds) Ans.

iii. Instruction Latency after Pipelining is introduced:

Execution stages and durations (with 5ns overhead each): 50 ns + 5 ns = 55 ns,

20 ns + 5 ns = 25 ns,

50 ns + 5 ns = 55 ns,

20 ns + 5 ns = 25 ns,

50 ns + 5 ns = 55 ns

Total instruction latency:

55 + 25 + 55 + 25 + 55 = 215 ns (Ans)

iv. Time to Execute 100 Instructions: Since the machine is pipelined, instructions are executed concurrently.

Maximum stage duration = max(55, 25) = 55 ns

Instructions per clock cycle:

1 (due to pipelining)

1 instruction / 55 ns = 1 / (55 × 10^(-9) sec)

= 1 / 0.000000055 sec

= 18,181,818 instructions/second

Converting to MIPS (Millions of Instructions Per Second):

18,181,818 instructions/second ≈ 18.18 MIPS

Time to execute 100 instructions:

100 instructions / 18,181,818 instructions/second = 5.5 μs (Ans)

v. Speedup Obtained from Pipelining:

Speedup = Non-Pipelined Time / Pipelined Time

Speedup = 19 μs / 5.5 μs ≈ 3.45

Pipelining achieves approximately 3.45 times speedup.

4. a) A virtual memory refers to a physical device that are used to store programs or data on a temporary or permanent basis.

b) A= b+c * d-e+f+a;

Using Accumulator (AC) and Temporary memory M(T)

LOAD b   AC = M (b)

ADD          AC = M (b) + M (c)

STORE T      M(T) = AC

MUL           AC = AC * M (d)

STORE T        M(T) = AC

LOAD e     AC = M (e)

SUB           AC = AC – M (e)

STORE T        M(T) = AC

LOAD f          AC = M (f)

ADD              AC = AC + M (f) + M (a)

STORE A      M(A) = AC

N.B  M(a) is the memory location.

5. a) Using Three-Address machine

A= b+c * d-e+f+a;

R1, R2, R3, R4 are registers

M(A) is memory location

ADD R1 b,c     R1 = M(b) + M(c)

SUB R2 d,e,    R2 = M(d) – M(e)

ADD R3 f,a     R3 = M(f) + M(a)

ADD R2,R3      R4 = R2+R3

MUL A, R1,R4         M(A) = R1 * R2+R3

b) Using Two-Address machine

A= b+c * d-e+f+a;

R1, R2, R3, R4 are registers

M(A) is memory location

MOV R1, b          R1 = M(b)

ADD R1, c           R1 = R1 + M(c)

MOV R2, d          R2 = M(b)

SUB R2, e           R2 = R2 – M(e)

MOV R3, f          R3 = M(b)

ADD R3, a           R3 = R3 + M(a)

ADD R2,R3        R4 = R2 + R3

MUL,  R1,R4       R1 = R1 * R4

MOV   A,R1       M(A) = R1

c) Using memory access as metrics, both Three-Address machine with the Two-Address machine have similar performance characteristics in Memory access frequency, Load/store ratio and Total memory access.

7.a) The term addressing mode refers to the way in which the apparent of an instruction is specified.

b) The Operand may be located in the following: i. Registers ii. Memory iii. Immediate values

c) i. Immediate Addressing Mode:

Example:

`MOV AL, 35H` (move the data 35H into AL)

ii. Register Indirect Mode:

Example:

`MOV AX, [BX]` (move the contents of memory location s addressed by the register BX to the register AX)

iii. Indirect Addressing Mode (Base + Offset):

Example:

`MOV AX, [SI + 05]`